`timescale 10fs/1fs
module TEST_RF;
	reg iClk, iRegWrite, iReset;
	reg [4:0] iReadReg1, iReadReg2, iWriteReg;
	reg [31:0] iWriteData;
	wire [31:0] oReadData1, oReadData2;

	RF U0(.*);
	
	initial begin
		#0 iClk <=1'b0;
		forever #0.5 iClk<=~iClk;
	end
	
	initial fork
	#0 {iRegWrite, iReset} <= 2'b11;
	#0 {iReadReg1, iReadReg2, iWriteReg} <= 15'b00000_00101_00101;
	#0 iWriteData <= 32'b1100;
	#1 iReset <= 1'b0;
	#2 iWriteReg <= 5'b00000;
	
	#3 iWriteReg <= 5'b00101;
	#3 iWriteData <= 32'b1111;
	#3 iRegWrite <= 1'b0;
	
	join

endmodule